1. Field of the Invention
The present invention relates to a solid-state imaging device and manufacturing method thereof, a driving method of a solid-state imaging device, and electronic equipment applied to a camera or the like that has the solid-state imaging device therein.
2. Description of the Related Art
A CMOS solid-state imaging device has been used as a solid-state imaging device. A CMOS solid-state imaging device has low power source voltage and low power consumption, and therefore is used in digital still cameras, digital video cameras, and further various types portable terminal devices such as cellular telephones with built-in cameras.
A CMOS solid-state imaging device is made up of a pixel region wherein multiple pixels that include photodiodes which are photoelectric converters and multiple pixel transistors are arrayed systematically and two-dimensionally, and a peripheral circuit portion that is disposed in the periphery of the pixel region. The peripheral circuit portion has a column circuit (vertical driving unit) to propagate the signals in the column direction and a horizontal circuit (horizontal transfer unit) to transfer the signals from each column propagated by the column circuit and so forth, sequentially to the output circuit. The multiple pixel transistors are often configured as three transistors which are a transfer transistor, reset transistor, and amplifying transistor, or configured as four transistors further including a selection transistor.
Recently, CMOS solid-state imaging devices that enable miniaturizing the pixel size without reducing saturation charge amount (Qs) or sensitivity have been developed (see Japanese Unexamined Patent Application Publication No. 2005-223084). This CMOS solid-state imaging device has a p-n junction of photodiodes formed within the semiconductor substrate, and has a transfer transistor having a vertical transfer gate electrode in the depth direction of the semiconductor substrate. A portion of the p-n junction of the photodiodes are formed so as to extend under the pixel transistors, whereby even if the pixel area is reduces, the area of the photodiodes can be expanded.
Japanese Unexamined Patent Application Publication No. 2006-506813 discloses a device dividing region wherein a polysilicon layer is filled in a substrate, or a polysilicon electrode layer negatively biased via a gate oxide layer is formed on the substrate front face, as device dividing regions. By applying a negative bias, dark current is suppressed.